Production of transistor arrays

ABSTRACT

A method of producing a transistor array, comprising an array of addressing conductors each providing the source electrodes of a respective set of transistors and at least part of a conductive connection between a respective driver terminal and said source electrodes; wherein the method comprises: forming a conductor layer on a support; and displacing a plurality of portions of said conductor layer relative to other portions of said conductor layer to create from said conductor layer at least (i) said array of addressing conductors and an array of drain conductors at said first level, (ii) conductor element islands in transistor channel regions at a second level, and (iii) one or more further conductor elements at a third level.

Transistor arrays are used, for example, in pixellated display devices to control the optical output of an array of pixels. The optical output of each pixel may be controlled by one or more transistors associated with the pixel.

A transistor array may be defined by a stack of layers including a conductor layer providing at least an array of addressing conductors, each addressing conductor providing at least part of a conductive connection between a respective driver terminal and the semiconductor channels of a respective set of transistors.

A conventional technique for producing an array of addressing conductors is to deposit a continuous layer of conductor material and then pattern the layer of conductor layer of material by removing selected portions of the conductor layer by e.g. photolithography.

It is an aim of the present invention to provide an alternative technique for producing an array of addressing conductors.

The present invention provides a method of producing a transistor array, comprising an array of addressing conductors each providing the source electrodes of a respective set of transistors and at least part of a conductive connection between a respective driver terminal and said source electrodes; wherein the method comprises: forming a conductor layer on a support; and displacing a plurality of portions of said conductor layer relative to other portions of said conductor layer to create from said conductor layer at least (i) said array of addressing conductors and an array of drain conductors at said first level, (ii) conductor element islands in transistor channel regions at a second level, and (iii) one or more further conductor elements at a third level.

In one embodiment, the second level is between the first and third levels.

In one embodiment, the distance between the first and second levels is smaller than the distance between the first and third levels.

In one embodiment, the method further comprises: depositing a substantially continuous layer of semiconductor channel material over the arrays of source and drain conductors, the conductor element islands and the further conductor elements; and selectively decreasing the conductivity of the layer of semiconductor channel material in one or more regions over the one or more further conductor elements at the third level.

In one embodiment, selectively decreasing the conductivity of the layer of semiconductor channel material in one or more regions over the one or more additional conductor elements comprises removing portions of the layer of semiconductor channel material in one or more regions over the one or more further conductor elements.

In one embodiment, the method further comprises forming a gate dielectric layer or stack of gate dielectric layers over at least the semiconductor islands, and forming an array of gate conductors over the gate dielectric layer or stack of gate dielectric layers for capacitative coupling with the semiconductor islands in at least the channel regions.

There is also hereby provided a transistor array, comprising; a first conductor pattern at a first level defining an array of source and drain conductors, each source conductor providing the source electrodes of a respective set of transistors and at least part of a conductive connection between a respective driver terminal and said source electrodes; a second conductor pattern at a second level defining an array of conductor islands in channel regions; a third conductor pattern at a third level, wherein the first, second and third conductor patterns form a complementary set of patterns; semiconductor channels between source and drain conductors in said channel regions; and one or more gate conductors capacitatively coupled to said semiconductor channels via a gate dielectric.

In one embodiment, the second level is between the first and third levels.

In one embodiment, the distance between the first and second levels is smaller than the distance between the second and first and third levels.

Embodiments of the present invention are described in detail hereunder, by way of example only, with reference to the accompanying drawings, in which:

FIG. 1 illustrates a plan view of a conductor array produced according to an embodiment of the present invention;

FIG. 2 illustrates the provision of gate lines and COM lines in combination with the conductor array of FIG. 1;

FIGS. 3(a) to 3(c) show cross-sections taken through lines A-A, B-B and C-C of FIG. 1, respectively;

FIG. 4 illustrates one example of a technique for producing a transistor array including the conductor array of FIG. 1; and

FIG. 5 schematically illustrates the connection of source and gate conductors to driver chips.

An example of a technique according to an embodiment of the invention is described for the example of a relatively simple transistor array for a pixellated display device, in which the transistor array defines only a single, respective transistor for each pixel. However, the technique may also be used, for example, for (a) the production of more complex transistor arrays that define a respective group of transistors for each pixel, or (b) the production of simple or complex transistor arrays for other pixellated devices such as sensors.

FIGS. 1 and 2 show the main conductor elements for only four pixels, but the technique can be used to produce large transistor arrays comprising transistors for more than a million pixels.

With reference to FIGS. 1 to 4, the technique involves depositing a thin layer of conductor material 12 on a substrate 14, which may for example comprise an uppermost layer of solid but relatively deformable material (such as a thermoplastic resin) on a relatively hard lower support. A relatively hard mold (harder than the layer of deformable material) is then used to forcibly depress selected portions of the conductor layer and the deformable layer in a direction substantially perpendicular to the plane of the first conductor layer and create conductor elements at three different levels, as shown by different types of hatching in FIG. 1. In this example, the first upper level defines (a) an array of source conductors 2 each providing (i) source electrodes 2 b of a respective column of transistors and (ii) an addressing line 2 a providing at least part of a conductive connection between said source electrodes 2 b and a respective terminal of a source driver chip 30; and (b) drain conductors 4 each providing a drain electrode 4 b in very close proximity (e.g. about 20 microns) to a respective source electrode 2 b and connected to a larger area conductor 4 a which can, for example, serve as a pad for an interlayer connection to a respective, upper pixel conductor (not shown). The second, middle level defines conductor islands 6 in the channel regions in between each pair of source and drain electrodes 2 b, 4 b. The third, lower level comprises the remainder of the conductor layer including all of the conductor layer in regions between source conductors 2 and drain conductors 4 outside the channel regions. In this example, the channel regions are those regions where conductor islands 6 are formed. The conductor islands 6 extend substantially the full width (distance along which the source and drain electrodes 2 b, 4 b are in close proximity) of the channel between the source and drain electrodes 2 b, 4 b of a transistor. As described below, semiconductor islands are formed in these channel regions and gate line conductors overlap said channel regions.

There is no conductive connection between any two of the three levels. There is no conductive connection between each conductor island 6 and the respective associated pair of source and drain electrodes 2 b, 4 b; there is no conductive connection between the conductor islands 6 and the conductor elements at the third, lower level; and there is no conductive connection between any of the source and drain conductors 2, 4 and the conductor elements at the third, lower level.

As illustrated in FIG. 1, the three conductor patterns at the first, second and third levels form a complementary set of conductor patterns; any two of the three conductor patterns exactly match the gaps in the remaining one of the three conductor patterns without any overlap of the three conductor patterns.

This process of displacing selected portions of the first conductor layer to create conductor elements at at least three different levels may be implemented, for example, by a technique comprising: providing an assembly including a thin gold film (as the first conductor layer) supported on a substrate via a layer of Parylene C, forcibly applying the protrusions of the stamp/mold to the upper surface of the assembly and down into the layer of Parylene C whilst holding the assembly at a temperature in the range of 120 to 140° C. (below the melting point of Parylene C), and then retracting the stamp/mold from the assembly. The stamp/mold produces breaks in the thin gold film at lines of discontinuity in the topography of the stamp/mold. This technique has been used before to facilitate the removal of selected portions of a metal film, but the use of this kind of technique in the embodiments of the present invention is characterised by retaining portions from the conductor layer (e.g. thin gold film) at three different levels in an array of transistors. In one example, the stamping/molding may be carried out as part of a roll-to-roll or spool-to-spool production process.

In the process described above, the source and drain conductors are defined without using any photolithographic technique, and without any wet etching.

Semiconductor channel material is deposited over the resulting structure by a technique that produces a layer of semiconductor material 18 that substantially conforms to the topography of the underlying structure. The semiconductor channel material layer 18 is then patterned to form semiconductor islands (FIG. 4(e)) so as to better prevent unwanted leakage currents between conductors via the semiconductor layer. The semiconductor channel material may, for example, be an organic polymer material, and the deposition technique may be spin coating.

The deposition of the semiconductor channel material may be preceded by one or more steps to improve the movement of charge carriers between one or more of the source and drain conductors and the semiconductor channel material. An example of one conventional technique involves forming a self-assembled monolayer (SAM) of suitable organic material on the source and drain conductors 2, 4 by a e.g. a technique that also results in formation of a SAM on the conductor islands 6 and on the further conductor elements at the third level.

Each conductor island 6 is connected to the respective associated pair of source and drain electrodes 2 b, 4 b (i.e. the pair of source and drain electrode between which the conductor island 6 lies at the second level) by a respective semiconductor island. It may be preferable to have only a short inter-level distance between the upper first and middle second levels in order to achieve a short channel length between the source and drain electrodes 2 b, 4 b of each transistor; and the retention of the conductor islands 6 may further improve the transport of charge carriers between the source and drain electrodes when the transistor is in an “on” state.

In contrast, it may be preferable to have a relatively large inter-level distance between the middle second and lower third levels in order to better avoid unwanted leakage currents, i.e. currents between source and drain conductors 2, 4 other than in the channel regions, particularly in regions underlying the gate conductors 8 but outside the channel regions. In one embodiment, the inter-level distance between the upper first and middle second levels is less than the distance between the middle second and lower third levels.

A gate dielectric layer or a stack of gate dielectric layers 20 are then formed over the resulting structure. A second conductor layer is then deposited over the gate dielectric layer(s) and patterned (by e.g. photolithography or laser ablation) to form (i) gate lines 8 each extending over the channel regions of a respective row of transistors and (ii) common voltage lines (COM lines) 10 each extending over the large area drain conductors 4 a of a respective row of transistors for capacitative coupling with those large area drain conductors. The COM lines 10 are all connected to a common power supply terminal. The second conductor layer may also comprise a metal layer.

Further layers (not shown) may be formed over the second conductor layer such as an insulating passivation layer, and an array of pixel conductors formed over the insulating passivation layer and each connected via a respective interlayer connection through the passivation layer and the gate dielectric to a respective drain conductor 4 a. Each pixel conductor may, for example, be used to control a respective pixel portion of an optical medium such as a light-emissive material, an electrophoretic material or a liquid crystal material.

As schematically shown in FIG. 5, each source line conductor 2 is connected to a respective terminal of one or more source driver chips 30 and each gate conductor 8 is connected to a respective terminal of one or more gate driver chips 32. Each transistor is associated with a unique combination of source and gate conductors 2, 8, whereby the potential at each drain conductor 4 can be controlled independently of all other drain conductors. The driver chips 30, 32 may be located, for example, on the same support substrate (e.g. plastic film) as that on which the transistor array is formed, or on separate components later connected to routing conductors provided on the same support substrate as the transistor array.

The above-described example involves the creation of three metal levels from a single conductor layer, but the same kind of technique may be used to create four or more metal levels from a single conductor layer.

In addition to the modifications explicitly mentioned above, it will be evident to a person skilled in the art that various other modifications of the described embodiment may be made within the scope of the invention.

The applicant hereby discloses in isolation each individual feature described herein and any combination of two or more such features, to the extent that such features or combinations are capable of being carried out based on the present specification as a whole in the light of the common general knowledge of a person skilled in the art, irrespective of whether such features or combinations of features solve any problems disclosed herein, and without limitation to the scope of the claims. The applicant indicates that aspects of the present invention may consist of any such individual feature or combination of features. 

1. A method of producing a transistor array, comprising an array of addressing conductors each providing the source electrodes of a respective set of transistors and at least part of a conductive connection between a respective driver terminal and said source electrodes; wherein the method comprises: forming a conductor layer on a support; and displacing a plurality of portions of said conductor layer relative to other portions of said conductor layer to create from said conductor layer at least (i) said array of addressing conductors and an array of drain conductors at said first level, (ii) conductor element islands in transistor channel regions at a second level, and (iii) one or more further conductor elements at a third level.
 2. The method according to claim 1, wherein the second level is between the first and third levels.
 3. The method according to claim 1, wherein the distance between the first and second levels is smaller than the distance between the first and third levels.
 4. The method according to claim 1, further comprising: depositing a substantially continuous layer of semiconductor channel material over the arrays of source and drain conductors, the conductor element islands and the further conductor elements; and selectively decreasing the conductivity of the layer of semiconductor channel material in one or more regions over the one or more further conductor elements at the third level.
 5. The method according to claim 4, wherein selectively decreasing the conductivity of the layer of semiconductor channel material in one or more regions over the one or more additional conductor elements comprises removing portions of the layer of semiconductor channel material in one or more regions over the one or more further conductor elements.
 6. The method according to claim 4, further comprising forming a gate dielectric layer or stack of gate dielectric layers over at least the semiconductor islands, and forming an array of gate conductors over the gate dielectric layer or stack of gate dielectric layers for capacitative coupling with the semiconductor islands in at least the channel regions.
 7. A transistor array, comprising; a first conductor pattern at a first level defining an array of source and drain conductors, each source conductor providing the source electrodes of a respective set of transistors and at least part of a conductive connection between a respective driver terminal and said source electrodes; a second conductor pattern at a second level defining an array of conductor islands in channel regions; a third conductor pattern at a third level, wherein the first, second and third conductor patterns form a complementary set of patterns; semiconductor channels between source and drain conductors in said channel regions; and one or more gate conductors capacitatively coupled to said semiconductor channels via a gate dielectric.
 8. The transistor array according to claim 7, wherein the second level is between the first and third levels.
 9. The transistor array according to claim 7, wherein the distance between the first and second levels is smaller than the distance between the second and first and third levels. 